Structured Design Methodology
Last Edit July 22, 2001
Introduction To The Overview
The Structured Design Methodology, as developed here for the design of
Bipolar, CMOS or BiCMOS logic arrays, applies to any array design effort
regardless of technology or vendor. The designer who follows this methodology
will ensure a smooth design flow between milestones that will help ensure
a successful design the first time.
The design flow is presented in this chapter at the introductory level.
Following chapters will detail specific areas such as timing analysis,
simulation and power computation.
Design Sequence - Pre-Capture
The Structured Design Methodology stresses a certain design flow sequence
of events, developed for use by the beginning array designer, the beginning
user of an Engineering Workstation (EWS) or the designer experienced in
both. Each step will be discussed in more detail after the design flow
is fully outlined.
Circuit functional specification
The circuit functional specification is the target specification; it
describes what it is that is to be implemented on one or more arrays.
This includes: a block diagram of the system or circuit, overall performance
requirements, I/O interface, testability, environmental and packaging
requirements. (See Table 2-1.)
Once the functional specification identifies the need for more than one
array, partitioning of the overall circuit modules to ensure proper boundary
conditions must be made and then the functional specifications of the
individual array circuits must be created. The specifications must be
defined to be independent of each other to allow parallel circuit development.
Note that there is no constraint at this point as to the product to be
used beyond operating specifications.
The technology of the array is defined by the performance requirements.
As a basic guideline, high speed requires ECL bipolar, slower speeds and
low power require CMOS, and moderate speeds and bipolar drive capability
without the price of bipolar power dissipation require BiCMOS. Where the
boundaries are is subjective and subject to continual evolution and change.
Table 2-1 Components Of The Target Specification
|Block Diagram Showing Modules and Their Interface to
Each Other and to the Rest of the System
|Functional Description of Modules
|Maximum Frequency of Operation
Circuit hardware specification
The circuit hardware specification is the planned hardware approach to
satisfying the target functional specification. For multiple array designs,
this may involve another level of specification, one specification for
each circuit intended for a different array. This implies that project
partitioning has been completed, and defines all required I/O and throughput
performance. (See Table 2-2.)
Table 2-2 Components Of The Hardware Specification
|Potential Array Series
|Modules Detailed into Functional Sub-Modules
|Functional Description of Sub-Modules
|Functional Block Sizing - Cell Counts (Rough)
|I/O Interface Details - Cell Counts (Rough)
|Toggle Frequency for I/O initial Packages
|Critical Path Throughput Estimates
A hardware architecture specification equates to PDL (program description
language) for software. It identifies modules and closely defines how
the modules will work together. HDL (hardware description language) and
VHDL have been developed to formalize this specification.
From this level of specification it is possible to estimate I/O signal
requirements and internal cell utilization. At this point, the estimates
are very rough and will only serve to allow a first cut at reducing the
number of arrays that need to be considered. Some compromises or engineering
tradeoffs may have been made, refining the functional specification.