Logic Design for Array-Based Circuits

by Donnamaie E. White

Copyright © 1996, 2001, 2002 Donnamaie E. White

 

Structured Design Methodology

Last Edit July 22, 2001


Compute the estimated power

Use the macro occurrence list compiled for cell utilization to compute power. Determine the worst-case current multipliers used by the array and what voltage variations will be used by the circuit for DC power computations. Review the AC power equation if AC power must be computed. ECL output macros use a termination current and that power element must be included with the DC power computation.

Different technologies use different methods to compute power as seen by the examples in Table 2-9.

Table 2-9 Example Technology Approaches To Power Computation - AMCC Arrays

  • Bipolar (pre-Q20000) uses a current dissipation for each
    macro regardless of operating frequency (DC power only).
  • CMOS uses internal and output macros and their operating
    frequency to find AC power dissipation.

  • BiCMOS uses a combination of these techniques, DC power
    for bipolar interface macros and AC power for internal macros.

  • Q20000 Series uses DC power for all macros and AC power
    computation for ECL inputs, Darlington outputs and all
    internal macros.


Some bipolar arrays have power-down capabilities that can reduce the current dissipated when macro output pins are not used (conditional geometry). Other arrays may have programmable overhead current. Before ac-tual placement, an estimate of the overhead current will need to be used.

Are the estimated power and estimated maximum
current acceptable for this design on this array?

Actual DC power computations and maximum current checks are available through the MacroMatrix AMCCERC after once the circuit has been captured on an AMCC-supported EWS or netlister. A worksheet is provided for AC power computation.

Compute maximum internal current

A maximum internal current may be specified for bipolar arrays. It is possible for the total core current to be computed and compared to array limits. It does not guarantee that the design will later pass layout row current limits. If the circuit internal core current is high and the cell utilization is also high, and other placement constraints are required, then the placement process will be difficult and may be unsuccessful.

Before placement, a global check is used, verifying that the core as a whole can handle the current required by the macros. A more detailed bus-check, or row, half-row, and quadrant current check, can be made after placement for those arrays which require this type of checking.

BiCMOS and CMOS arrays typically have no internal current limit. The development of three-layer metal arrays reduced the concern for this check for bipolar arrays as well, leaving the final control of the power used in the design to be a function of the ability to keep the junction temperature of the packaged part within limits.

Make the final package selection

Make the final package selection based on the array chosen and the estimated power. Refer to the Packaging Brochure from the chosen vendor.

For packages with internal power and ground planes, the package selected will control the placement of added power and grounds if the use of package signal pins is to be avoided. A package must accommodate all signal pins required for the circuit plus any signal pins required by added power and grounds not placed to connect to the internal power/ground planes of the package.

When a package has no internal bonding planes, the selected package signal pins must be sufficient to include all circuit signals and all added power and grounds.

Review the array for any other pads that need package signal pins before making the package selection. The Q20000 Series arrays have four fixed pads, two for the thermal diode anode and cathode and two for the AC speed monitor. These array pads must reach external package signal pins, decreasing what is available for the circuit proper.

Compute the junction temperature

Compute the estimated junction temperature based on the power dissipation, the packages available that meet specifications and the operating environment, including any heat sinking and air flow as specified in the functional specifications. If possible, several options should be evaluated.

The allowed packages for an array should also have their thermal coefficients for junction-case (Qjc) and junction-ambient (Qja) specified. Tables or some other means of computing the coefficient for case-ambient (Qca) as a function of the heatsink, the array, the package and airflow should also be provided. For most military applications, Tc can be maintained at 125oC. For most Commercial applications, Ta can be maintained at 70oC.


Read "Theta" for Q:

Military: Tj = Pd * Qjc + Tc

Commercial: Tj = Pd * Qja + Ta

with Qca = Qjc + Qca


With the completion of both timing and power analysis, changes in macro options, or optional functions within the circuit can be evaluated and the speed-power curve managed before full schematic capture and simulation have been performed.

Optional - Bonding diagram (custom bonding), Pin-out request

As an option, a bonding diagram (pin out) request can be submitted to the vendor for approval

Both pin out requests and placement requests can be initiated by the designer and both must be approved by the vendor after layout and Back-Annotation evaluation.

Review the design submission requirements

Review the requirements for the array series design submission as specified by the vendor.

  • Are schematics required?
  • What schematic format is required by the vendor?
  • What simulation must be run and submitted?
  • What other procedures are requested by the vendor?

Clarify what is to be done to actually perform a design submission to your vendor.

Copyright @ 2001, 2002 Donnamaie E. White, White Enterprises
For problems or questions on these pages, contact dew@Donnamaie.com

CAD/SW Engineer
Technical Writer (synthesis, place and route)



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