Sizing the Design - Selecting the Array
Last Edit July 22, 2001
Functional Specification - A Closer Look
The functional or target specification is the first level of description
of the project that may encompass one or more arrays when the design is
partitioned. There may be a specification tree with the total project
at the top node and individual circuit blocks or modules detailed underneath.
Topics included in a functional specification are listed in Table 3-1.
At this early stage, a functional description of what is to be
accomplished is created along with some of the top-level circuit requirements.
For the partitioned project (multiple arrays), the individual array specifications
would include a description of array interfacing.
Interconnection between arrays is faster when done with ECL. When choosing
single or dual (differential) rail ECL use the following guidelines:
- If the arrays will be placed on the same board and will be adjacent
to each other, single rail (non-differential) ECL may be acceptable.
- If the arrays will communicate across a backplane or be remote on
the board, differential ECL may be required.
- Differential ECL is required if the operating speeds exceed the maximum
frequency specifications for single rail ECL.
The potential need for differential ECL should be indicated at the functional
specifica tion level.
Partitioned circuits should attempt to balance
the distribution of I/O and internal cell usage
between the different arrays while maintaining
critical paths within one array if possible.
This is still the rule to follow - no matter how big the
It is also a good guideline for how to break up a 6-8 milllion
gate array into top-level blocks - keep the critical paths inside
the block if possible.
Interblock connections today are what interarray connections
Table 3-1 Components of The Functional specification
|Block diagram to the module level- including any partitioning into
more than one array
| Description of the boundaries between the modules and the rest
of the system
| Initial sizing of the I/O interface by type - ECL, TTL, etc.
| Functional Description of the Modules
| Description of the interface between the circuit modules - busses,
control, critical interconnects
| The overall performance requirements
| - - - the maximum frequency of operation
| - - - target clock speed (per clock)
| - - - path propagation delay requirements set by modules external
to this design
| I/O toggle rates
| Synchronous/asynchronous signals
| Allowed or available power supplies
| Power restrictions
| Physical size restrictions
| Environmental requirements -Commercial, Military, Industrial, Other
| Packaging requirements
| Derating for junction temperature
| Prioritized design objectives
Design criteria that are considered as hard (inflexible) specifications
should be clearly documented as such. Specifications that might be alterable
should also be clearly identified. If a tradeoff or judgment call needs
to be made during the remainder of the design project, such information
can save time and possibly the project.
Overall design objectives should be clearly identified and documented.
These include optimization for speed, power or die size, which translates
to minimized inter nal cell utilization and minimized I/O utilization.
Since these objectives are in conflict, they should be prioritized.
As a last step, there should be a careful design review of the circuit
and sys tem functional specifications, and the partitioning