Logic Design for Array-Based Circuits

Copyright © 1996, 2001, 2002 Donnamaie E. White

• Table of Contents
  
• Preface
  
• Overview
  
• Chapter 1 Introduction
• Chapter 2 Structured Design Methodology
• Chapter 3 Sizing the Design
  • Functional Specification - A Closer Look
  • Review the Available Arrays
  • Architectual Specification or Hardware Specification
  • Array Sizing
  • Cell Capabilities
  • Array Architecture
  • Netlist
  • Example: AMCC Interface Options
  • Example - AMCC Arrays - Power Supply Options
  • Interface Cell Functionality
  • Examples
  • Internal Cell Functionality
  • Multi-Cell Macros
  • Hard and soft macros
  • Refining Interface Requirements
  • Adding Extra Power and Ground Macros
  • Dual-Function I/O Macros
  • Example - Simultaneously Switching Outputs
  • Thermal Diodes
  • The AMCC Speed Monitor
  • Final Interface Cell Utilization
  • Drivers
  • Exercises
• Chapter 3 Appendix: Case Study in Sizing a Design
  • Target Array: AMCC Q20080 (1994 Data)
  • Solution - Q20000
  • Selecting a Flip/Flop - First Pass
  • Selecting the ECL Output
  • Clock Input
  • 16:1 MUX
  • Parity Tree
  • Review Status so far
  • Exercise
  • Simultaneouly Switching Outputs
  • Fanout Loads
    • Select Lines for 16:1 MUX
    • Reset Loading
    • Clock
    • Static Driver
  • Review of Size - Second Pass
  • Package Size
  • Problems
  • Alternative Solution
  • Power
  • Further Thought
  • The Schematics
• Chapter 4 Design Optimization
• Chapter 5 Timing Analysis for Arrays
• Chapter 6 External Set-up and Hold Times
• Chapter 7 Power Considerations
• Case Study: DC Power Computation
• Case Study: AC Power Computation
• Chapter 8 Simulation
• Case Study: Simulation
• Chapter 9 Faults and Fault Detection
• Chapter 10 Design Submission
• ASIC Glossary
  • Glossary A-D
  • Glossary E-K
  • Glossary L-R
  • Glossary S-Z
  • Symbols

Sizing the Design - Selecting the Array

Last Edit July 22, 2001

Cell capabilities

Cells for each array have different capabilities. The cells for different array series, same technology (bipolar, BiCMOS or CMOS), from the same vendor may also differ widely in the approach used in their design and in their functional complexity.

Example - AMCC cell capabilities

An internal cell for the Q5000 Series can support a complex D flip/flop, a 3:1 MUX and D flip/flop, a triple latch, two simple (no RESET, single output) D flip/flops, or triple 2:1 MUXs with common select. The Q20000 Series internal cell alone cannot support a D flip/flop. S- and L-option D flip/flops use two cells while H-option D flip /flops require three.

The Q20000 Series internal cell is roughly comparable to a half-cell for the Q5000 Series if size of function alone is considered as the basis for comparison. The logic cell for the Q20000 Series is defined as the smallest partition possible and each internal cell supports one Turbo macro output. Turbo is a Q20000 feature that provides high drive (18 loads) with less power and less skew.

Cell types and resources

The vendor data sheet and design guide or design manual should clearly identify cell types and the number of each on each array in the series. Any restrictions in the use of the cells, either utilization limits or cell count limits should also be readily available.

Included in these descriptions should be a measure of cell functionality, either in a table summarizing the array cell capability or through the macro library documenta tion.

As a part of the cell resources identification, the vendor should be supply a clear description of the fixed power and ground pads and procedures to added additional power and ground pads. These added power and ground macros usually reside on an I/O cell and pad and can affect the number of cells left for circuit signals.

Example - AMCC Cell types

The basic AMCC logic array is composed of two classes of cells: the internal cells, which is composed of logic (L) and memory (M) cells for bipolar arrays or basic (B) cells for BiCMOS arrays; and the perimeter cells composed of input, output or bidirec tional (I/O) cell. Older AMCC arrays had buffer cells internally and specialized input or output-only interface cells. An array may or may not have specialized I/O cells. AMCC cell types are shown in Table 3-7.

The QM1600S (now the QM1600T) was the first of the AMCC arrays to incorporate memory on a logic array.

Table 3-7 Cell Types

INTERNAL:	Logic,	Basic,	Buffer,	Memory
PERIPHERAL:	Input,	Output,	I/O,	Special-I/O

Refer to the cell resources table for an approximate idea of the array cell capacity for three series and note the differences. Cell resources for the Q24000 Series are shown in Table 3-8, for the Q5000 Series in Table 3-9 and for the Q20000 Series in Table 3-10. Note that no two series are alike!

Table 3-8 AMCC Q24000 Series Arrays - Cell Resources

Array Name	Internal B Cells	I/O Cells	Pads
Q24280	6880	300	256
Q24140	3360	226	226
Q24091	2268	160	160
Q24060	1440	132	132
Q24021	540	80	80
Q24008	190	66	44

Usage restrictions: Refer to the Q24000 Design Manual for details.

Table 3-9 AMCC Q5000 Series Arrays - Cell Resources

Array Name	Internal L Cells	I/O Cells	Output Limit	Memory Cells
Q5000T	352	160	120	-
Q3500T	242	120	-	-
Q1300T	84	76	-	-
QM1600T	114	106	-	2 (1240 bits)

Table 3-10 AMCC Q20000 Series Arrays - Cell Resources

Array Name	Internal Cells	I/O Cells (For Signals)	I/O Cells (Fixed) (1)	Signals - PLL Related	Signals - Loop FIlter (2)
Q20120	3414	198	4	-	-
Q20080	2044	162	4	-	-
Q20045	1227	128	4	-	-
Q20P025	595	76	4	13	8
Q20025	733	100	4	-	-
Q20P010	177	54	4	13	8
Q20010	267	66	4	-	-

* Two pads are used by the AC Speed Monitor and two by the thermal diode.
** Only for the largest arrays, 100_LDCC for the Q20P010 and 132_LDCC for the Q20P025
Add last four columns to find total I/O cells and pads.

Array Name	ECL Outputs Limit	TTL Outputs Limit	PLL Power/Ground	Power/Ground (1)
Q20120	172	100	-	78
Q20080	130	80	-	52
Q20045	100	64	-	52
Q20P025	45 (2)	45 (2)	8	26
Q20025	80	48	-	36
Q20P010	23 (3)	23 (3)	8	20
Q20010	50	24	-	32

(1) Add last two columns to find total number of fixed power and grounds.
(2) 51 for external loop
(3) 34 for external loop

Copyright @ 2001, 2002 Donnamaie E. White, White Enterprises
For problems or questions on these pages, contact dew@Donnamaie.com