Design Optimization
Last Edit July 22, 2001
Example of silicon efficiency
As an example of high-functionality silicon-efficient macros, the AMCC
REG00 universal register is the equivalent of four 4:1 MUXs and four D
F/F or 8 macros and is available in several libraries. In the Q5000 library,
it uses 4.5 internal cells whereas the individual 4:1 MUX and D Flip/Flop
macros would use 8 internal cells. The number of inter-macro interconnects
is 15 and their delays are kept constant for each occurrence of the MSI
macro due to the required placement pattern. REG00 is a soft macro in
the Q5000 library and a hard macro in another.
Table 4-4 Basic Macro-Selection Guidelines *
| Path Type |
Use these macro types: |
Penalty: |
| Clock paths |
High fan-out drivers
High speed, minimum
skew macros |
more power
more cells
more power |
| Fast paths |
High-speed, minimum
skew macros |
more power |
| Loaded paths |
High fan-out drivers
Parallel structures |
more power
more cells
more power
more cells |
| Slow paths |
Low-power, slower macros |
(less power)
(less cells) |
| Average paths |
Standard macros |
-------- |
* For libraries with high-speed, low-power, standard and driver macros.
Comprable tables can be generated for libraries with other combinations
of variations, versions and options.
Alternative implementations
One way to ensure that the best version of a critical path has been created
with any given library is to create more than one solution. Alternative
implementations should be reviewed within the confines of a specific set
of prioritized design objectives. They should always be evaluated for any
critical path.
Paths (partial circuits) can be captured and simulated for detailed comparison
of timing, including timing check analysis using the current workstations.
Some jury-rig of connectors or dummy loading may be required depending
on the peculiarities of the CAD/CAE workstation chosen and the part of
the circuit being captured. This is a minor inconvenience in exchange
for which the designer can easily perform timing analysis, such as checking
on pulse width distortion, set-up and hold violations and path delays.
Examples
As an example of the value of checking various implementations, a test
circuit was given to students, applications and macro design engineers
to implement using the Q5000 library. The design objective was stated
as speed at all costs. The students (unfamiliar with the macro library)
produced circuits running at 125-145MHz. Applications engineers produced
a version running at 183MHz. The array-macro designers produced a version
running at 235MHz. The variable was macro library familiarity; no custom
macros were allowed.
The case study in the previous chapter was another example. It showed
two different implementations of that circuit, one with an output toggle
rate of 350MHz and one with 600MHz - the only difference was the output
macro.
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