Last Edit July 22, 2001
Internal Net Delays
The delay in a heavily loaded net tends to be longer than the macro intrinsic
delay, the delay through the macro that drives the net. The net delay
is a result of the electrical effects of fan-out load, wire-OR load and
the capacitance of the metal interconnect length. Wire-ORs if allowed
in the library will add to the delay in the net with both an electrical
load and with additional metal.
Front-Annotation delays (pre-place and route) due to metal length for
a large array are on the average larger than for a small array. This is
reasonable since the side to side distances are larger for the larger
array. The break-up of heavily loaded paths into identical parallel paths
can result in significant propagation delay improvement, regardless of
Table 4-5 Components Of Internal Net Delays
|Internal Net Delays
- electrical fan-out load
- electrical wire-OR load
- capacitive load of the metal etch
Fan-out loading is the same regardless of the array size. A macro driving
6 loads on a large array would see the same load if the circuit were placed
on a smaller array.
Wire-ORs when allowed
Some array libraries allowed dot-connects such as wire-ORs or wire-ANDs.
These may save gate delays but add a wire or metal length penalty. A wire-OR
driven by four macros and outputting to six other macros has the metal
equivalent of a ten output net - using lumped Front-Annotation computations.
This is considered to be a heavily loaded net. The added net delay will
probably exceed the "saved" gate delay. The use of dot-connects should
be carefully evaluated.
Verify that they are allowed on the schematics before evaluating their
usefullness. They may be allowed on some arrays and not on others from
the same vendor. For example, the AMCC Q5000 has wire-ORs but the Q20000
bipolar and Q24000 BiCMOS arrays do not allow their use.
Figure 4-2 Optimization - Speed
Optimization - Speed Considerations