Bit-Slice Design: Controllers and ALUs

by Donnamaie E. White

Copyright © 1996, 2001, 2002 Donnamaie E. White

 
 

Preface

Table of Contents

1. Introduction

2. Simple Controllers

3. Adding Programming Support to the Controller

4. Refining the CCU

5. Evolution of the ALU

6. The ALU and Basic Arithmetic

7. Tying the System Together

Glossary

 

 

Simple Controller

Last Edit Ocober 10, 1996; July 9, 2001


Start Address

If the controller is a CCU, the start address of each microroutine is derived from the current machine instruction. At the minimum, an instruction register must be added between the data bus and the counter data inputs to store this instruction. A load control bit must be added to the microword for the instruction register, which must load prior to the counter load (see Figure 2-5). This scheme requires that the op code equal the high-order bits of the start address, with the low-order bits tied to logical "0". This is necessary to allow the starting addresses to be separated by the mini mum number of addresses required by the longest microroutine.

Figure 2-5 Basic CCU (x, number of bit in op code; n, number of bits in counter address)

basic block diagram adding instruction register to counter and memory

Assume that no machine instruction is anticipated to take more than 16 microinstructions to execute. Also, assume a 12-bit address and a 4K PROM memory. The op code must then be no more than 8 bits in length, and the lower 4 bits of the counter data inputs must be tied low (or to logical zero). Sixteen steps are are allowed per microroutine, and up to 256 different start addresses are possible with this configuration.

The clock pulse required by the controller has not changed. Remember also that the width of the memory is not a function of its depth.

This scheme is adequate if:

  1. There is sufficient room in the PROM memory
  2. Spare locations are acceptable
  3. No microroutine exceeds 16 steps
If a microroutine exceeds 16 steps, it would overrun a start address, reducing the number of op codes possible (reduced by however many start addresses are overrun); this may still be acceptable. Short routines leave discontinuous unused areas scattered throughout the PROM memory (fragmentation); this may also be acceptable.

Mapping PROM

If fragmented space and reduced numbers of available op codes are not acceptable, one solution is to add a mapping PROM between the instruction register and the counter. The op code is the address into the map, which in turn outputs the full start address of the microroutine to the counter, as shown in Figure 2-6. Start addresses may now be assigned at any location in the PROM memory rather than requiring them to be equidistant from each other, and microroutines may be compacted in this way to delete excessive fragmented space. (It is, however, a good idea to allow some unused areas within the PROM to allow for enhancement changes to the system.) The final placement of the microroutines in the production PROMs should be done after the debug cycle to minimize mapping PROM changes. This is where a development system is used to advantage.

Figure 2-6 Mapping PROM

diagram of a mapping PROM showing decode path

Another feature may be added once a mapping PROM appraoch is chosen. The mapping PROM may be made larger than required for normal running and contain address lines driven by switches to allow a Privileged State, where all op codes are valid, and a Normal State, where certain op codes are invalid, "trapping out" to an error trap address in the control memory. The control memory would not necessarily be larger than before.

The CCU is shown in Figure 2-7. A fairly reasonable control system has been constructed which is acceptable is all of the microroutines are simple sequences.

Figure 2-7 CCU with Mapping PROM

 

For information about this file or to report problems in its use email dew@Donnamaie.com

Copyright © September 1996, 1999, 2001, 2002 Donnamaie E. White White Enterprises

CAD/SW Engineer
Technical Writer (synthesis, place and route)



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