Bit-Slice Design: Controllers and ALUs

Copyright © 1996, 2001, 2002 Donnamaie E. White

Preface

Table of Contents

1. Introduction

• Pre-Introduction
• Selection of the Implementation
• Microprogramming
• Advantages of LSI
• The 2900 Family
• Language Interrelationships
• Controller Design
• Constructing the CCU

2. Simple Controllers

• Sequential Execution
• Multiple Sequences
• Start Addresses
• Mapping PROM
• Unconditional Branch
• Conditional Branch
• Timing Considerations
• Pipelining
• Improved Architecture

3. Adding Programming Support to the Controller

• Expanded Testing
• Subroutines
• Nested Subroutines
• Stack Size
• Loops
• Am29811
• Am2909/11
  
• CASE Statement (Am29803A)
• Microprogram Memory

4. Refining the CCU

• Status Polling
• Interrupt Servicing
• Implementation - Interrupt Request Signals
• Vector Mapping PROM
• Next Address Control
• Am2910
• Am2910 Instructions
• Control Lines
• Interrupt Handling
• Am2914
• Interconnection of the Am2914

5. Evolution of the ALU

• Instruction Formats
• Control Unit Function
• PC and MAR
• Improving ALU Speed
• Adding Flexibility
• Am2901

6. The ALU and Basic Arithmetic

• Further Enhancements
• Instruction Fields
• Instruction Set Extensions
• Sample Operations
• Arithmetic -- General
• Multiplication with the Am2901
• Am2903 Multiply

7. Tying the System Together

• Expanded Memory for the Am2903
• MUX Requirements
• Status Register
• Am2904

Glossary

Table of Contents

Last Edit October 25, 1996; May 1, 1999; July 7, 2001

• Preface

1. Introduction
   • Pre-Introduction
   • Selection of the Implementation
     • Architecture
     • Size
     • Word LEngth
     • Instruction Set
     • Speed
     • Tradeoffs
   • Microprogramming
   • Advantages of LSI
   • The 2900 Family
   • Language Interrelationships
     • HIgh-Level Language
     • Assembly Level Language
     • Machine Level Language
     • Microprogramming
     • Microprogram Storage
     • Format
     • Development Systems
   • Controller Design
     • A simple Computer
     • Constructing the CCU
       • Hardwired Design
       • Microprogrammed Design
       • Cost Effectiveness
2. Simple Controllers
   • Sequential Execution
   • Multiple Sequences
   • Start Addresses
   • Mapping PROM
   • Unconditional Branch
   • Conditional Branch
   • Timing Considerations
     • Sequential Timing
     • Branching
     • Pipelining
     • Pipeline Branch
     • Improved Architecture
       • No Branch
       • Improved Branching
3. Adding Programming Support to the Controller
   
   • Expanded Testing
   • Subroutines
   • Nested Subroutines
   • Stack Size
   • Loops
     • Tristate Lines
     • Start Address Stirage
     • Counter
     • Am29811
   • Am2909/11
     
   • CASE Statement (Am29803A)
   • Microprogram Memory
     • Am27S27
     • Sample Design
     • Sample Design 2
4. Refining the CCU
   • Status Polling
   • Interrupt Servicing
     • Polled Interrupt
     • Vectored Interrupt
   • Implementation - Interrupt Request Signals
     • Interrupt Storage
     • Polled Interrupt
     • Vectored Interrupt
     • Vector Mapping PROM
     • Next Address Control
   • Am2910
   • Am2910 Instructions
     • Jump Zero (JZ)
     • Continue (CONT)
     • Jump Map (MAP)
     • Conditional Jump (CJP)
     • Conditional Jump Vector (CJV)
     • Load Counter and COntinue (LDCT)
     • COND Jump PL (JRP)
     • COND JSB PL (CJS)
     • COND JSB R/PL (JSRP)
     • Conditional Return (CRTN)
     • Repeat PL CNTR not 0 (RPCT)
     • Push COND LD CNTR (PUSH)
     • Repeat Loop, CNTR not 0 (RFCT)
     • Test End Loop (LOOP)
     • COND JUMP PL and POP (CJPP)
     • Three Way Branch (TWB)
   • Control Lines
     • Register Load
     • Test Enable
     • Carry In
     • Stack and Enable
   • Interrupt Handling
     • Clearing Interrupts
     • Interrupt Enable
     • Nested Interrupts
     • Status Fance
     • Other Embellishments
   • Am2914
   • Interconnection of the Am2914
     • Single Unit
     • Interconnection
     • Microprogram Interrupt
     • Machine Level Interrupt
5. Evolution of the ALU
   • Instruction Formats
   • Control Unit Function
   • PC and MAR
   • Improving ALU Speed
     • Current Instruction Execution
     • Scratchpad Registers
     • Generalized ACC
     • Generalized PC
   • Adding Flexibility
     • Input MUX A
     • Output MUX
     • Status Lines
     • Shift and Rotate
     • Control Bits
     • Double Precision
     • Additional Modifications
   • Am2901
     • Source Control
     • Function Control
     • Destination COntrol
     • Interconnection
6. The ALU and Basic Arithmetic
   • Further Enhancements
   • Instruction Fields
   • Instruction Set Extensions
     • Shifting
     • Three-Address Operation
   • Sample Operations
     • Increment
       • Am2901 Version
       • Am2903 Version
     • Byte Swap
       • Am2901 Version
       • Am2903 Version
       • Am2901 Hardware Version
       • Am2903 Hardware Version
   • Arithmetic -- General
     • Addition
     • Subtraction
     • Multiplication
       • Unsigned Binary
       • Multiplicand Negative
       • Multiplier Negative
       • Both Negative
       • Result
   • Multiplication with the Am2901
     • The Algorithm
   • Am2903 Multiply
     • Unsigned Multiply
     • Twos Complement Multiply
7. Tying the System Together
   • Expanded Memory for the Am2903
   • MUX Requirements
   • Status Register
   • Am2904

• Glossary
• Index

Copyright © September 1996, 1999, 2001, 2002 Donnamaie E. White White Enterprises